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Thursday, January 21, 2010

PGDCA First Semester Examination, 2009-10, Computer Organization

D-4089
PGDCA First Semester Examination, 2009-10
Paper : First
Computer Organization
Time Allowed : Three Hours
Maximum Marks : 50

Note : Attempt Question 1 which is compulsory (carries 14 marks) and any other four questions(carries 9 marks each) from the rest. Five questions are to be answered in all.

1. (a) Define any four of the following : (4)
(i) Radix of a number system.
(ii) Word
(iii) Microprocessor
(iv) Multiplexer
(v) Cache bandwidth
(b) Convert the gray code 1101 to binary. (1)
(c) What is a parity bit in error detecting code? (1)
(d) Represent NAND gate as an inverter. (1)
(e) A line printer is capable of printing 132 characters on a single line, and each character is represented by 7-bit ASCII code. How many bits are required to print each line? (1)
(f) Explain the operation of JK flip flop. (1)
(g) State DeMorgan's theorem. (1)
(h) What is a counter? (1)
(i) Represent the following expression on K-map (2)
f=(A+B)(A'+B)(A'+B')
(j) What is the significance of virtual memory? (1)
2. (a) What is the concept of locality of reference? explain. (2)
(b) Differentiate between Spatial, Sequential and temporal locality of reference. (2)
(c) With the help of neat diagram explain how paging and segmentation is implemented. Also give the structure of map tables in both methods. (5)
3. (a) Distinguish between combinational and sequential circuits? Give examples of each. (2)
(b) Implement the following function (5)
F(a,b,c,d)=sigma M(1,3,5,6,8,9,11,12,13,15)
Using (i) Basic logic gates (ii) Using 1 of 8 MUX
(c) Give the logic implementation of 8X4 bit ROM using decoder of a suitable size.
4. (a) Write short note any three of the following :
(i) Assemble language programming
(ii) Flip Flops
(iii) Belady's Anomaly
(iv) Cache memory
(b) Differentiate between the following : (1.5+1.5)
(i) High order memory interleaving and Low order memory interleaving.
(ii) Half adder and full adder
5. (a) Why are computers memory system typically built as hierarchies. (2)
(b) If the address bus of a microprocessor is 16 bit wide what shall be the size of its memory map? (1)
(c) What is cache hit/miss? Give an expression for hit ratio. (4)
(d) What is PROM? Can a ROM device be considered as a combinational circuit. (2)
6. (a) Describe pipelining. (2)
(b) What is the difference between machine language and assembly language. (1)
(c) Write the characteristic table of a simple SR FF designed using NOR gates only. Derive its excitation table, characteristic equation and draw the corresponding State Diagram. (6)
7. (a) What is meant by State reduction? Which state of the Given states can be reduced? (3)
(b) Methodically design the following counter: (6)
-> 1-> 3 -> 5 -> 7 -> 9 -> 11 ->
8. (a) With the help of a neat block diagram explain how any computer functions. (4)
(b) Explain the addressing modes of an 8 bit microprocessor with examples. (5)


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